The invention relates to an integrated circuit, comprising an output stage with an input which is coupled to a first and a second gate electrode of a first and a second current channel, respectively, and an output which is connected to a first and a second supply terminal via the first and the second current channel, respectively, which output stage is arranged to switch over, under the control of a signal on the input, from a first state (L) in which the first and the second current channel are conductive and non-conductive, respectively, to a second state (H) in which the first and the second current channel are non-conductive and conductive, respectively, the output being coupled to the first gate electrode via a series connection of a Miller capacitor and switching means. An integrated circuit of this kind is known from U.S. Pat. No. 5,051,625.
The first current channel in this circuit is formed by the channel of an NMOS transistor; the second current channel is the channel of a PMOS transistor. In the first state, i.e. the "logic low" state, the channel of the NMOS transistor connects the output to the low supply voltage applied to the first supply terminal. In the second state, i.e. the "logic high" state, the channel of the PMOS transistor connects the output to the high supply voltage applied to the second supply terminal. To this end, the voltage on the gate electrodes of the NMOS transistor and the PMOS transistor is logic low.
Upon switching over from the second to the first state, the voltage on the gate electrodes is raised from logic low to logic high. The voltage on the output then decreases because the channel of the NMOS transistor starts to conduct whereas the channel of the PMOS transistor ceases to conduct. If switching over from the second to the first state is very fast, disturbances occur. The speed of switching over, and hence the occurrence of disturbances, is dependent on the degree of loading of the output.
The Miller capacitor provides retrocoupling of the voltage on the output to the gate electrode of the NMOS transistor. Such retrocoupling opposes the increase of the voltage on the gate electrode of the NMOS transistor. This opposition is greater as the rate of decrease of the voltage on the output is higher. Because the rate of decrease of the voltage on the output itself is dependent on the voltage on the gate electrode of the NMOS transistor, due to the characteristic of the NMOS transistor, the rate of decrease is thus limited. The Miller capacitor thus controls the rate of decrease and limits the disturbances occurring upon switching over from the second to the first state.
Upon switching over from the first to the second state, the channel of the PMOS transistor starts to conduct whereas the channel of the NMOS transistor ceases to conduct. The rate at which the channel of the NMOS transistor ceases to conduct is then slowed down by the Miller capacitor, whereas the PMOS is already conductive. As a result, a short-circuit current starts to flow from the first to the second supply terminal. This current causes interference pulses on the supply terminals and increases the power consumption of the circuit.
In an embodiment of the prior art circuit the channel of a further NMOS transistor is connected in series with the channel of the NMOS transistor. In response to the signal on the input, the channel of the further transistor is also rendered non-conductive when the channel of the NMOS transistor is rendered non-conductive.
This prevents the short-circuit current, although this is not disclosed in the cited publication (U.S. Pat. No. 5,051,625), but has the drawback that a substantial surface area in the integrated circuit is thus taken up. As it forms part of the current path of the output stage, the further NMOS transistor already has to be constructed so as to be rather large. Moreover, the NMOS transistor and the further NMOS transistor must be twice as large as the NMOS transistor in the original output stage if the output stage is to retain the same drive power as the original output stage comprising a single NMOS transistor.